Week of 11/21/2022
Completed schematics, and PCB design for a basic 4-bit register that can be cascaded to create a 16-bit register. Ordered printed PCBs from Elecrow Bazaar.
Week of 11/28/2022
Completed the design for the ALU, still waiting to receive the ordered PCBs for the 4-bit registers
Week of 12/05/2023
Received the first batch of PCBs for the 4-bit registers, but they are not functional as registers on there own since in the design I forgot to add the global reset signal. I decided to use these PCBs as a part of the Program counter as the main board will control resets.
Week of 12/12/2023
Completed the design for the Program Counter and ordered the printed PCBs.
Week of 12/19/2023
Completed design for the Tristate Buffer and ordered printed PCBs from Elecrow Bazaar. Received PCBs for ALU and updated 4-bit register
Week of 12/26/2023
Finished 3D object model for connecting clip for PCB prototyping boards
Week of 1/16/2023
Received all the PCBs that are required for the construction of the program counter. Began the construction of the Program Counters and completed construction of the ALU.
Week of 1/23/2023
Received the final PCBs that are required for the construction of the program counter, and completed the construction of the PC.
Week of 02/06/2023
Optimized the design for the registers that includes a functional reset signal as well as a better timing method using buffered input. In addition I optimized the timing to occur only once per 16 bit register, and created a controller to convert a register to a shift register.
Week of 02/13/2023
Completed the design for the programmable ROM interface, and began design for an FPGA development board to begin the new FPGA series.
Week of 02/20/2023
Completed the design for a 2-4 decoder and a 3-8 decoder that can be cascaded into larger size decoder. Additionally created an signal bus to connect the CPU signals to the appropriate component.
