Building a Discrete Computer

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Basic 16-Bit Register: Designing a Discrete Register

by · Published · Updated

12/04/2022

Schematic of 4-Bit Register (without global reset)

What is a Registers

A register is a small, high-speed memory unit within a computer’s central processing unit (CPU). It is used to store and quickly access frequently used instructions and data. The CPU uses registers to hold data that is currently being processed, as well as to store the results of these operations. Registers are much faster to access than main memory, so the CPU is able to work more efficiently by using them to store and quickly access data that it needs to process. This allows the CPU to quickly retrieve and process instructions, which helps the computer run more efficiently and faster.

The Basic Design

The general purpose register utilizes the basic mechanisms of the D-Flip Flop as explained in “Basic 16-Bit Register: SR latches, D Latches, and D Flip Flops“. To put it simply, a D latch is a device that stores a data value when an enable signal is active, and holds onto that value when the enable signal is inactive. In the case of the D-Flip Flop, the clock signal serves as the enable signal, loading a value when high, and latching the value when low. Another important design component is that the CLK signal is ANDED with a LOAD, so the flip flop only functions when the signal is active (otherwise the clock signal is forced to low).

Design of 1 Bit Register using gated logic
Example Timing Diagram for a 1 Bit D Register with a LOAD signal and a Rising edge triggered enable signal

The above design suffers from a serious flaw: The register will load the value during the entire positive pulse of the clock, while an ideal circuit would load once, on the rising edge of the clock. To address this issue is to place an RC circuit immediately following the clock signal, as shown in the circuit architecture below. When the clock first reaches the a high value (5V) the current through the capacitor will be at a maximum and all 5V will be seen across the resistor (and simultaneously at the D-Flip Flop in parallel with the resistor). This point is shown in the RC graph below when VR=5V and VC=0V at time 0. As time progresses, the capacitor will start to charge, and the current will decrease, thus decreasing the current through the resistor. This results in an exponentially decreasing voltage to the circuit, which will allow me to accurately load data only on the rising edge of the clock.

RC Timing Circuit

The timing constant, represented by the Greek letter “τ,” is approximately equal to the product of resistance (R) and capacitance (C) in a circuit. The chosen MOSFETs (2N7000) have a switching voltage of approximately 3V, so the clock will only trigger when the period is slightly less than 1τ. The appropriate values of RC timing depend on the frequency of the clock. For example a clock with a frequency of 32KHz (1/32,768 cycles/seconds) may use a rising edge that is roughly (1/100,000 seconds), so a resistor value of 100 Ω with a capacitor value of 0.1 µC can be used (100 * 10^-7 = 10^-5). These values need to be carefully considered as a smaller rising edge may be limited by confounding variables of real life application.

Timing diagram displaying the original clock (black), the rising edge (orange), and the operation cutoff for the transistors (blue ~=3V)

Designing the Schematic in Autodesk Eagle

To transfer the schematic to Autodesk Eagle, I first converted the logical circuit to one that consists only of transistors, resistors, and capacitors The only two gates needed to create for this circuit was a NAND gate and an AND gate. As explained in a previous post the transistor equivalents of these two logic gates are shown below:

NAND gate and AND gate architecture utilizing N-Channel MOSFETs

To create a 1-bit D Flip Flop with a load signal and a clock signal on the rising edge, I combined the MOSFET equivalent circuit with the logic diagram and created the following schematic in Eagle.

Schematic for Single Bit of 4-Bit Register Design

Both the inputs and the outputs are connected to pins that can be externally accessed and connected to the bus. To create the complete 4-bit register I simply cascaded 4 of these data registers, and linked the output to pins on the device. Additionally, I added LEDs connected to MOSFETs (with the Q as the gate signal) to the design to show the bitwise results of the data transfer.

Breadboarding the Circuit

To ensure the success of the design and implementation of the PCB, I first tested the circuit in a simulation using Logisim to verify the logic of the design. After verifying the logic, I proceeded to test the functionality of the circuit on a breadboard by constructing a 1-bit register using NAND and AND gates. I tested the design for the 4-bit register on the breadboard by testing a single 1-bit register. Since the 4-bit register is simply a cascaded version of the 1-bit register, testing the functionality of the 1-bit register was sufficient to ensure the success of the overall design.

AND and NAND gates modelled on breadboard (left) and a 1-bit register breadboard design (right)

In the process I utilize Ben Eater’s 555 timer that has two modes: oscillating mode, and debug mode. The oscillating mode (indicated by top LED) oscillates like a normal clock would with a variable speed that is controlled by a potentiometer. The debug mode allows me to create manual clock pulses that are controlled directly by button input, allowing to step through the cycles. These two modes are selected via a switch.

After connecting the proper clock (from the rising edge RC circuit), data (controlled by a button circuit), and load (controlled by a button circuit) lines, I was able to test the cases of the register. To test the board I utilizes button inputs, by testing some key cases:

  1. Holding the load button (yellow button) without touching the data button (blue button) to ensure the output LED does not turn on
  2. Holding the load button, and holding the data button through one clock cycle when output LED is off. After one cycle has elapsed releasing the data bit to ensure the LED turns on, then releasing the load button to ensure the data is still latched
  3. Holding the load button, without pressing the data button through one clock cycle when output LED is high. After one cycle has elapsed ensure the output LED turns off and that that value is latched. Then releasing the load button to ensure the data is still latched
  4. Try pressing the data button while the load button is high to ensure previous data is latched (no change is seen on the LED)
  5. Try disabling the clock (debug mode) and ensure the value of the output LED stays latched for any combination of load and data signal input
Complete 1-bit register testing environment

Designing the PCB Board in Autodesk Eagle

In this project, all PCB designs share the same structure and organization. Each PCB is organized in a 4-bit modular manner and includes four rows of two transistors, with the necessary resistors along the edge of the rows. The bottom of the PCB includes input data pins and voltage/ground pins that are accessible through hole pin headers. The top of the PCB includes data out pins and LEDs that display the current output state, also accessible through hole pin headers. Additionally, each PCB includes a global LED voltage input that can be adjusted externally using a potentiometer to control the brightness of the LEDs. Lastly any PCB with a clock input will include an LED that flashes at the same frequency as the clock input.

Basic PCB design for the project (left) and PCB design for the 4-bit data register (right)

Since each PCB will contain 4 bits of data in a 16 bit system I will need to cascade four of them in a row to create each 16 bit component of the computer. Additionally each PCB board will be constructed with through hole components, that I will individually solder to the board upon arrival of the PCBs.

Design Update

As a final addition to the design, I included a global reset input that clears the data output line when the reset pin is taken to a high state. This is useful for implementing a global reset button that clears all data from the entire computer in the final design. This can be done by simply ANDing the output with the inverted clear signal, ensuring the output is only cleared when the reset signal is active. On the schematic and board this involved adding a single transistor to invert the reset signal and twelve extra transistors (three for each bit of the register) to create the AND gates immediately before Q.

1- bit Register architecture with a Reset signal input
Updated schematic of 1-bit data register section with global reset signal
Updated PCB with global reset pin

One final functionality of the register that I would like to add is a tri state buffer logic to control when a register writes out to the bus. This requires the use of CMOS logic, which utilizes both N channel and P channel MOSFETs. I have ordered about 30 or 40 P channel MOSFETs but they are not set to arrive for a while, so I held off on adding these to this version of the register. I have decided to create a separate PCB that takes in all 16 bits of the register and handle the write control logic from that board. I will discuss this in a separate post as I would like to receive and test the P channel transistors before I solidify any designs.

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