Connecting to the Bus: Designing a Tristate Buffer
12/22/2022
What is a bus?
In computer architecture, a bus is a system of communication channels that enables the transfer of data between different components within a computer or between computers. It can be thought of as a kind of “highway” for data, allowing different components to exchange information and work together.
All components of my computer will be connected via a connection to a single bus, and each component can access the data on the bus by using a load signal, which “pulls” the data from the bus when it is active. The input mechanism of my data registers illustrate this point. The load signal is combined with the clock signal using an AND gate, such that the clock signal is only active for the register when the load signal is active. When the load signal is inactive, the clock signal is also inactive, preventing the register from accepting new data from the bus. However, when the load signal is active, the clock signal becomes active as well, allowing the register to load data from the bus and update its internal state.
However, writing data to the bus is more complex, as only one device can write to the bus at a time to avoid conflicting signals that could potentially cause a short circuit. To solve this problem, a tristate buffer is often used, which has three states: high, low, and high impedance (also known as high Z). The tristate buffer allows a device to output its data onto the bus in a controlled and coordinated manner, preventing interference between multiple devices. To write data to the bus, the device activates its tristate buffer, driving the data onto the bus. When the device is not actively outputting data, the tristate buffer can be switched to the high impedance state, effectively disconnecting the device from the bus and allowing other devices to access it. The specific mechanisms and further explanation of the tristate buffer will be detailed below.
The Tristate Buffer
As explained above a tristate buffer is a device that is vital for the design of a bus as it allows a high and low state to control the bit that is being written to the bus, in addition to a high impedance (high Z) state that essentially disconnects the device from the bus. The basic tristate buffer includes a data input, an enable signal, and an output signal. When the enable signal is brought high the data can pass though to the output, and when the enable signal is low the buffer is in a high Z disconnected state:
Designing a tristate buffer:
The tristate buffer being designed requires the use of CMOSFETs, which utilize both N-channel and P-channel MOSFETs. These two types of MOSFETs differ in the type of material used in their channels, with N-channel MOSFETs featuring channels composed of N-type material, characterized by an excess of electrons, and P-channel MOSFETs featuring channels composed of P-type material, characterized by an excess of holes. The importance of complimentary MOSFETs in this design is highlighted by the two essential differences between the two:
- Current is allowed to flow in an N channel MOSFET when the gate has a high voltage whereas current is allowed to flow in a P channel MOSFET when the gate has a low voltage
- N-channel MOSFETs are good at conducting current when they are “on,” but have a high resistance when they are “off.” P-channel MOSFETs are good at blocking current when they are “on,” but have a low resistance when they are “off.”
For the implementation of the tristate buffer, the complimentary P-channel MOSFET being used is the BS250, which exhibits similar switching characteristics to the 2n7000 N channel MOSFET. The tristate buffer is typically constructed in a totem pole configuration, with two P-channel MOSFETs positioned above two N-channel MOSFETs, and the output taken from the junction between the P-channel and N-channel MOSFETs.
While the totem pole configuration of the tristate buffer only requires the use of four MOSFETs, I have discovered that the BS250 P-channel MOSFETs necessary for this design are difficult to obtain and significantly more expensive than the 2n7000 N-channel MOSFETs that I have been utilizing. As such, I have developed an alternative design that achieves the same result using only one P-channel MOSFET, one N-channel MOSFET, and two logic gates, each of which is constructed using two N-channel MOSFETs. To create this design, I first drew the basic structure of the tristate buffer using a P-channel and N-channel MOSFET, and then represented each of the three states (Low, High, and High Z) in the design.
From here I created a logic table using two arbitrary variables, LOAD and Q, and determined the desired values of the OUT variable for each combination of LOAD and Q. I then referenced the previous sketch to determine the necessary gate voltages to achieve the desired OUT states, and selected the NAND and AND gates as the most suitable options for implementing these values
The above circuit employs eight MOSFETs in its design, comprising two for the primary structure, two for the NAND gate, three for the AND gate, and one for the NOT gate on the Q signal. By implementing a few simplifications, I was able to reduce the total number of transistors from 128 to 96. Specifically, I converted the AND gate, which required three transistors, into a NOR gate with two transistors. Additionally, I moved the NOT gate from the Q signal, which is unique to each bit of the 16-bit tristate buffer, to the LOAD signal, which is common to all bits. These changes were made possible by utilizing a few fundamental principles of logic gates:
- A NAND gate followed by a NOT gate is the same as an AND gate
- Two NOT gates at the inputs of an OR gate is the same as a NAND gate
- A NOR gate followed by a NOT gate is the same as an OR gate
- two cascaded NOT gates cancel each other out
Thus the final design of a one bit tristate buffer includes a NAND gate, a NOR gate, a single NOT gate, and two MOSFET transistors that comprise of the backbone:
Designing a Tristate Buffer Schematic:
The above circuit can easily be transferred to Autodesk Eagle. I chose to construct the 16 bits of the tristate buffer on a single board, as opposed to the four-bit designs I have previously used, since each bit now only requires six transistors. The schematic for this design includes input (Q) pins, output (OUT) pins, a load pin, a single NOT gate for the LOAD signal, and 16 individual bit tristate buffers. This approach allows for a more compact and efficient implementation of the tristate buffer.
Designing a Tristate Buffer PCB Board:
Having generated the Eagle Schematic, I moved on to the board design stage. One useful feature of Autodesk Eagle is the “Design Block” tool, which enables me to copy and paste a layout from the schematic and maintain consistent wire connections on the board. This significantly reduced the time required for board design, as I only had to wire up one bit of the tristate buffer and then copy and paste the design block 16 times to complete the rest of the circuit. The ability to quickly replicate the design of individual bits allowed for a more efficient and streamlined approach to the overall board layout. Additionally, I decided to omit the inclusion of LEDs, as both the bus and the output component of the computer already feature LEDs for displaying data.
Basic Architecture of my Computer:
Some components, such as RAM and isolated data registers, can both read from and write to the bus using load and write signals from the control logic unit. These components are known as “external registers.” Other elements, referred to as “internal registers,” are permanently connected to their parent device and can only read from the bus using a load signal from the control logic unit, but always output to their parent device. These internal registers do not require tristate buffers, but still require an activatable load signal. Examples of internal registers include those within the ALU and Program Counter. The parent devices (ALU and Program Counter) will require tristate buffers in order to write results to the bus. This hierarchical structure allows for efficient communication between the various components of the system.
