Building a Discrete Computer

Build a transistor level computer with me!

Project Updates 02/15/2022

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02/15/2022

There has been a long delay between my previous post and this one because I have been experiencing significant delay between waiting for my PCBs to come in and finding the time to complete the soldering of the hardware components with classes. I will talk about a new project that I will be doing in parallel to this project involving FPGAs that will allow me to post more content and create more designs while I wait for the components.

There has been a significant delay between this post and my previous post due to the long wait for my printed circuit boards to arrive and the lack of adequate time for soldering the hardware components alongside attending classes this semester. However, I am excited to share that during this delay, I have started working on an additional project utilizing field-programmable gate arrays (FPGAs) in parallel to my current venture. This new undertaking will allow me to produce and share more content and designs while awaiting the arrival of the necessary components. I will discuss the details later in this post, and in the next few posts.

Current Status

Currently I have completed the design for the Basic Register, Arithmetic Logic Unit, Program Counter (PC), tristate buffer, and the register interface for the CPU. I have also finished soldering the Program Counter as well as the data bus, and have connected these components to each other to create a functional interface. Additionally I have finished soldering the ALU PCB board itself but have not yet created the internal registers A and B that feed into the unit. Because of this I have not yet implemented it to the main functional interface that includes the PC and bus.

Completed Program Counter (Bottom six panels) with a data bus, and signal bus (top left panel)

In the design considerations for my RAM/ROM interface I decided that I needed a shift register to minimize the pins needed to flash data from my computer to ROM (via an Arduino nano board). For this reason I have modified one of my basic 8-bit registers to test the potential functionality of a shift right register. I achieved this by feeding the output of each bit into the input of the next bit and determining the ideal RC timing constant that facilitates a single shift per time cycle. I found that the shift operation functioned effectively for rightward shifts at frequencies up to 1 MHz, but it is important to note this was done on a breadboard which may have significantly altered performance.

Hardware test for shift register

Additionally, I plan to enhance the structure and functionality of the shift register by incorporating three control signals: shift left, shift right, or load. These control signals would enable the user to select a normal register setting, where data comes from the bus, a shift right setting, where data comes from the adjacent bit on the left, and a shift left setting, where data comes from the adjacent bit on the right. This will require the creation of a rudimentary 3-gate logic circuit that receives the control signals, and which can be easily hand-soldered onto small prototype PCBs and connected to the register using wires. Although this feature may not be essential at my current stage in the project, it could be advantageous for future logical applications.

The following picture illustrates the various connections that I have soldered to the back of the computer which allows communication signals between PCBs and the various VCC, clock, and GND connections. I have color coded these wires with VCC, LEDVCC, GND, clock, control signals, data lines all having there own color to make it easier to debug, and verify the connections.

Wired Connections on the back of the Program Counter Interface Panel

Current Plans

The next big undertaking in the project is the design of a ROM and RAM interface to allow a location to both store the program I would like the computer to run, as well as store variables, data, and data types such as the stack. I would like to finish soldering the current hardware components and ensure they work well together before I complete this design as this design will use the other components such as the data bus and the PC to work.

My plans for the ROM/RAM interface is to include an Arduino Nano that can easily flash my assembly code from my computer to a ROM ship, then have the hardware complete the writing of the data from ROM to RAM. I will keep track of the ROM/RAM addresses using the PC, and the data to be stored in the ROM will be first shifted into a 16 bit shift register (to limit the number of pins used on the Arduino nano), then pushed into ROM.

Preliminary Design for RAM/ROM interface (will be discussed further in a later post)

Addition of FPGA to my Project

Since the components take such a long time to design, order and solder I have decided to start a new project in parallel to this project with a colleague where I will code a custom designed FPGA development board using Verilog that implements the same components that my main project uses. Whenever I design a component for the original project I will simultaneously code it on the FPGA to show a more modern solution to CPU design.

Although I will explain in much more depth in a later post in short an FPGA (Field Programmable Gate Array) is a sort of integrated circuit that can be programmed or reprogrammed after manufacturing to implement a wide range of digital logic functions. This means it is not limited to a single hardware path like normal designs but can rather be physically changed by the programmer. This is done through configurable logic blocks, programmable interconnects, and other resources that can be used to build digital circuits and systems. The concept and design of the board will be described in my next few posts as I get the exact details of the project planned.

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