Building a Discrete Computer

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Arithmetic Logic Unit: Designing a 4 Bit Binary Adder

by · Published · Updated

1/1/2023

Basic Design of the 4-Bit Binary Adder

The gated mechanism of a binary adder, as previously discussed, involves the use of a full adder circuit that accepts three inputs: two inputs and a carry in. This circuit produces an output, as well as a carry out, by cascading two half adders, which each consist of a XOR (Exclusive OR) gate and an AND gate. The full adder is able to accept a carry from a preceding adder and output a carry that can be inputted into a subsequent full adder, allowing for the cascade of multiple full adders. In my design, I have implemented a cascade of four full adders to add four bits of the numbers. The final computer will cascade four of these boards to create a 16 bit adder

Design for a 4-Bit Binary Adder

Adding Subtract Functionality

The binary adder will employ the Two’s Complement system of binary subtraction, as previously mentioned, to represent signed numbers (representation that allows both positive and negative numbers). The Two’s Complement method involves taking a number as a positive binary value, inverting all the bits, and adding one to the result to obtain the negative value. For example, to represent -7 in Two’s Complement, the positive representation of 7 (0111) is taken, all the bits are inverted (1000), and one is added to the result(1001). Employing the principle A-B=A+(-B) a number can be converted to the negative value then added to another number to effectively subtract the two numbers (result will be in two’s compliment).

It is important to note that the most significant bit of the Two’s Complement value represents the sign of the number, limiting the magnitude of the value that can be stored. Specifically, while an unsigned 16-bit number can represent values from 0 to 65,536, a signed Two’s Complement 16-bit number can represent values from -32768 to 32767.

The implementation of a Two’s Complement system on a hardware level is relatively straightforward through the use of a XOR gate. The XOR gate functions such that when one of its inputs is 0, the value of the other input is simply passed through the gate, and when that input is 1 the value of the other input is inverted at the output. This can be visualized by analyzing the Logic Table for the XOR gate:

Logic Table for XOR gate; When A is 0 B is passed to the output, when A is 1 B is inverted at the output

My design will include a Subtract Enable (Bit A from the table above) bit that when active (1) will perform subtraction and when inactive (0) will perform addition. The Subtract Enable bit will be the input of the XOR that dictates its behavior: a value of 0 allows the value of the other input to pass (bits are not inverted), while a value of 1 inverts to output (bits are inverted). Additionally the subtract enable signal can be tied to the carry in of the first adder to add 1 to the One’s Complement to create Two’s Complement when the enable signal is instantiated

Designing a Schematic

The schematic design was created by converting the above logic gates to a system of N-Channel MOSFETs. The conversion of the AND gate, NAND gate and OR gate is described in a previous post. Additionally the design needs an XOR (Exclusive OR) gate that can be created using MOSFETs according to the following diagram

The XOR gate implemented using N-channel MOSFETs has the following behavior:

  • When both inputs are 0, the left side of the circuit is disconnected from ground resulting in a value of 5V to T3. This means current can flow through T3 shorting the overall circuit which will result in a value of 0V at the output
  • When either of the inputs is 1, the left side of the circuit is connected to ground, and the transistor T3 is off (no current flows). In this case, the output is 1 only when the right side of the circuit is not connected to ground. The combinations 01 and 10 result in an output of 1.
XOR Gate Constructed from N Channel MOSFETs

It is sometimes difficult to understand a schematic when only presented with text so I have created a table below to show the four possible states of the XOR gate. Green Lines have a current running through them and red lines have no current.

Four states of the XOR gate

With all this in mind the design of the schematic is simply a matter of converting the logic gate circuit to an all transistor circuit:

1-Bit Binary Adder with Subtract Enable Signal
Full Implementation of a 4-Bit Binary Adder

Designing the Board

The final step for this part of the ALU is to design a circuit board that can be printed for the actual computer. As I have done for the previous parts the design for the board will follow the same layout as my previously created components. This means the ALU unit will include eight input pins (four for each input register to be added) and four output pins. Additionally the board includes four rows of transistors and resistors, output LEDs, voltage/clock input pins, and a carry out pin to cascade multiple boards together.

Final Board design for the 4-bit binary add/subtract module

Final Design Considerations

The final design will include each of these designed boards that take input from two separate registers (registers A and B). The design for a 4 bit register was discussed in a separate post. The board will need to be connected to a tristate buffer to connect to the bus, but will not need to regulate input as it constantly outputs the result of register A plus register B.

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