12/2/2022: Computer Architecture
The following image shows my planned architecture for the computer. This is of course subject to change as I continue the project, but it is always good to have a basic architecture to build off of. The components of the computer are as follows:
Address and Data Bus: Universal busses (wires that hold data) that each component have the option to read or write to. Arrows pointing toward the bus means the component can write to the bus, and arrows away from the bus means the component can read from the bus. For each bus only one component can write, and only one can read at a given time. The address bus holds the current address that the CPU is performing, and the data is for data transfer.
ROM: Read Only memory. I will use an EEPROM (Electronically Erasable Programmable ROM) that will include the control lines at each address. This dictates the behavior of the computer. Gets the address from the address bus and writes to the CL.
CL: Control Logic. Essentially a CPU that controls signals to other devices to dictate the behavior of the computer.
PC: Program Counter: Incrementor that holds the current operation address that the CL is running. Can either increment, or jump to a certain address
SP: Stack Pointer: Points to a given address in the stack which is an allocated location in memory
RAM: Random Access Memory: The overall memory of the computer
REGA/REGB: General purpose registers
ALU: Arithmetic Control Unit: Module to do basic calculations between register A and register B
OUT: Simply an LED display that displays the state of the data bus
