Major Design Updates
06/17/2023
Introduction
First and foremost, I apologize for my recent hiatus from posting, I have recently started at a new position, which has considerably limited the time I can allocate to this project. However, I have now settled into my new role and have been able to allocate a few hours each week to work on this project. While progress may be slower, I am optimistic that I will be able to provide more frequent updates to this site going forward.
During my absence, I was fortunate enough to acquire invaluable knowledge and skills that I am eager to integrate into my project. As a result, I have made a decision to start fresh, starting a complete redesign of my CPU. While preserving the fundamental schematic designs and concepts, the focus of optimizations will predominantly be directed towards the PCB design, as well as the holistic physical layout.
One significant change involves transitioning from Autodesk Eagle to the Altium Designer which I recently learned comes at no cost with a student license. In the new design I will explore the realm of advanced routing techniques, harness the potential of smaller components, implement hierarchical mounting, and conduct intricate calculations. A key focal point of these design modifications will be optimizing delays and impedances, thereby elevating the overall efficiency of my CPU’s performance.
New Components to Optimize Area and improve connectivity
In the original design, I encountered several unforeseen issues that I aim to resolve in v2 of the project. Firstly, the sheer size of the components posed a challenge. The accompanying image below illustrates only a single 16-bit register and the data bus which measures out at over 2-feet high. Continuing in the same manner for implementing my planned system with 16 registers, multiple counters, an ALU, control logic, RAM, and ROM plus some display peripherals and IO would have resulted in an overwhelmingly large structure. Apart from the evident constraints on storage and convenience caused by this size limitation, it also necessitates extensively long wire connections, leading to increased overall resistance and undesirable delays.
The overall size of the original design is a result of both the size of the TO-92 resistor package and all the wasted space between boards, as can be seen in the image below.
In addition to the size-related challenges, my design also encountered reliability issues. The use of soldered wire connections on the back of the boards posed difficulties in tracking and organizing the connections. The proximity of these wires to other solder sites and the inclusion of unnecessary wire lengths also led to unreliable connections and unexpected delays. Furthermore, the presence of these wires made the device inherently fragile, and I frequently found myself going back and resoldering hard to reach connections.
In the pursuit of enhancing the design of the new PCBs, a significant improvement in area will be seen simply by adopting a smaller and more efficient package type for the MOSFET, resistor, and LED components. Transitioning from the relatively larger TO-92 package (measuring 4.6 mm x 3.9 mm), to the compact SOT23 package (measuring 3.0 mm x 2.5 mm). I found that in the design of a new register PCB using these new components (along with a few other space saving techniques) I was able to get the PCB down to roughly half of the original size.In addition these components that I am using are all surface mount components, which will hopefully help with some of the unreliable connections on the original design (sometimes I had to wiggle a few FETs to get a design to work)
Another technique that I will be implementing to solve some of the pitfalls of the original design is that I will implement custom container boards to hold and connect each of the 4-bit components. The smaller boards will mount to the surface of these boards using castellated holes, create a direct soldered connections between the IO of the mounted PCB and the container board. This means all the tedious wire connections will be replaced with onboard traces, and I will be able to minimize the amount of wasted space on the board.
The Future of the Project
With these new design considerations in mind I hope to take the best designs from V1, and implement them in a more efficient manner on V2. I will begin by recreating the registers, then move to recreating the counters, RAM, and bus interface.
