Programmable ROM Design
03/08/2023
What is ROM
Read Only Memory, or ROM, is a highly reliable form of non-volatile memory that retains stored information even when the device is powered off. ROM devices are typically pre-configured at the hardware level by the manufacturer and can only be read from. To enhance the versatility of ROM devices, Erasable Programmable ROM, or EPROM, was developed. EPROM enables users to reconfigure the memory by exposing a window on the top of the device to ultraviolet light in a process called memory burning.
For my project, I will be utilizing the latest type of ROM, Electronically Erasable Programmable ROM or EEPROM. This type of ROM functions similarly to EPROM, but allows for reconfiguration of the memory through the use of pulsed voltages on configuration pins instead of ultraviolet light. This technology is highly flexible and can be used in a wide range of applications, making it an ideal choice for my project.
Why Does my Computer need ROM
The primary memory system utilized by modern computers is known as Random Access Memory, or RAM. RAM is the superior option due to its high-speed processing capabilities, which are significantly faster than ROM. Additionally, RAM has a greater storage capacity than ROM, enabling it to accommodate a larger volume of data. However, it’s important to note that RAM is volatile memory, meaning that all stored information is lost when the device is powered off.
To optimize the performance of my computer, I will be implementing an interface system that combines both RAM and ROM. By leveraging the non-volatile nature of ROM and the superior speed of RAM, I can achieve a reconfigurable system that maintains its information on power down, but still works at a decent speed.
The process entails programming the ROM using the computer and completing a flash cycle. Once the cycle is complete, the data is transferred from ROM to RAM. Given the non-volatile nature of ROM, I only need to flash each program once, then can simply transfer data from ROM to RAM on each power up. To facilitate easy transfer of program information to RAM during each power-up, my ROM interface board will feature a convenient button. This process ensures optimal performance while minimizing the need for repetitive programming tasks.
Design Considerations for ROM interface
To achieve a memory size that is compatible with modern computing requirements (at least 16 bit addressable memory), I have made the decision to incorporate ROM and RAM components into my computer that are not solely comprised of discrete components. This approach was necessary as it is almost impossible to design these elements with the required memory capacity using discrete components.
To ensure optimal performance, I will be utilizing 16-bit addressable Integrated Circuits for both the RAM and ROM components. In addition, I will interface my computer with an external computer for programming purposes using an Arduino Nano. Despite these choices the ROM interface will still utilize some of the peripherals on the computer such as program counters, shift registers, and storage registers during the flash cycle. I may choose to implement some of these elements using discrete components in the future.
The specific ROM chips I will use in my design is the X28C512P which is a 64K x 8 bit addressable EEPROM chip. This means that each chip will have a 16 bit address, and will hold 8 bits or 1 byte in each memory block. Since the RAM will have 64K x 16 bit blocks I will need to utilize two ROMs with the first ROM being the first 8 bits of each block and the second being the last 8 bits of the block.
Designing the ROM Interface
The fundamental principle behind the PCB design is to establish connections between the Arduino Nano and EEPROM pins to the necessary components. The Arduino Nano will manage all required timing and signal placement. Furthermore, the design will incorporate two flags that will indicate the programming cycle’s status. The flip-flop-designed flags can be conveniently set or reset. The two flags that are integrated into the design are the ROM programming in-process flag and the RAM programming in-process flag. These flags will both hold a HIGH value while the RAM/ROM programming cycle is active and a LOW value when it’s not. By using these flags, the interface can employ combinational logic to determine when different cycles can occur.
The basic structure of the interface will follow the following simplified model, which will be explained in more detail in the next section:
Flash Cycle for the ROM Interface
The ROM Flash cycle will follow a systematic procedure to program each line of the ROM using serial data through a shift register, while simultaneously keeping track of the address through the PC. Here is a detailed breakdown of the process:
1) The programming cycle is initiated when the ROM Write signal is generated by pressing the ROM Program Button. This will activate the ROM Programming flag and light up the LED, indicating that the process has started.
2) Initialization of the program begins by resetting the Program Counter.
3) The data from the Program Counter is output to the Address Register through the bus. This is achieved by enabling the tristate buffer on PC and enabling the load signal on the Address Register. Since the address register is directly wired to the address pins, this sets the ROM address to be written to.
4) On each clock cycle, a bit of each data line is pushed to the 16-bit shift register. This is achieved by placing the serial bit on the shift register line and enabling the left shift.
5) Once the 16 bits of the shift register are loaded, the contents of the shift register are output to the bus. The content of the bus is then pulled to the data lines of the ROM chip, and simultaneously the write enable on the ROM is enabled, saving the data lines at the address dictated by the address register.
6) The Program Counter is incremented.
7) If the program is not at the last line, the process goes back to line 3 and repeats the load cycle. Otherwise, if the program is on the last line, the ROM in process flag is reset to indicate that the ROM has been programmed (Should be done on the low of the clock), and the Program Counter is reset.
The above-described cycle will begin when the program button is pressed. It starts by setting the flag to indicate that the ROM is being programmed, and simultaneously resets the Program Counter to start writing at index 0. Steps 3 to 7 are the actual program cycle. During each cycle, the address from the Program Counter is pulled into the Address Register, and 16 bits of serial data (from a bitstream that represents the software) are shifted into a shift register. The data is then loaded into the ROM at the address indicated by the Address Register by instantiating the load pin on the ROM. This process continues until the end sequence.
Extra Pins Not Involved in Programming Cycle
In the ROM programmer design, there are a few extra pins that have been integrated to provide additional functionalities beyond the ROM write cycle. These pins are utilized to supply voltage lines to the computer, take in a clock, and interface with the RAM module. Here is a detailed explanation of each pin:
Green Lines: The green lines on the model represent the signals and voltage lines that are provided to the computer. Previously, the computer was powered by pins on a breadboard. However, to simplify the design, the 5V pin on the Arduino nano and the ground pin are now used to power the computer. These lines also include the LED voltage line for the flags, and the clock signal to ensure the ROM system is synchronous.
Orange Lines: The orange lines indicate the system involved in the button that sets the RAM programming in process flag to high. When the Initiate RAM Write button is pressed and simultaneously, the ROM programming in process flag is low (meaning that the ROM programming is not in process), the RAM programming in process flag will be set to high.
Purple Lines: The purple wires indicate that the external RAM controller can gauge the state of the flag to determine when the chip should be active (when the RAM programming in process flag is HIGH). Additionally, the other purple line is a means for the external RAM controller to reset the flag to indicate that its programming cycle has completed.
Schematic Design for the ROM Programming Interface
The schematic design for the ROM programmer follows a similar technique used in designing other components of the computer. The design includes connections between the appropriate pins on the ROM chip and the Arduino Nano board, ensuring proper communication between the two.
Furthermore, the two flag registers have been implemented using simple SR latches, as described in a previous post. To ensure that the signals default to low when not set, the inputs of the SR latch have been designed with a pull-down resistor.
The data lines, address lines, and externally accessible pins have been designed as through-hole pins. This not only simplifies the design but also ensures ease of use and accessibility for any potential future modifications or repairs.
Lastly the system implements four pin buttons that allow the user to control the programming cycle for both the RAM and ROM module.
Board Design for the ROM Programming Interface
The board design for the ROM programmer has been crafted using a similar technique as in the past. The transistors have been stacked in a row of two along the right side of the board, creating a clean and organized layout.
Moreover, the placement of the Arduino Nano has been carefully considered to ensure easy accessibility. It has been positioned in a location where it can be easily plugged into a computer without any hindrance, enabling seamless programming of the ROM chip.
The overall design of the board not only ensures efficient use of space but also provides a user-friendly interface. The layout has been designed to minimize the complexity of the board, making it easy to understand and modify if needed.
