Register Design: Build 2

07/30/2023

In Build 2, the primary focus revolves around optimizing size and organization. The design of the individual register panels closely follows the blueprint of Build 1, which you can explore further in the following link.

Register Structure

Following the standard set by the design of Build 1, each 16-bit register in Build 2 is subdivided into 4-bit boards connected to a single load and output signal. However, where the Build 2 design diverges is primarily in the structure of the board. Instead of mounting the registers to blank perf boards, with soldered through hole pins, and external wiring, I creating a dedicated PCB (Printed Circuit Board) . This board incorporates etched interconnects to replace the soldered wiring, and allowed direct surface mounting of the board through castellated holes.

The result of this design is efficient assembly and confidence in the interconnects between boards. Additionally to allow for customizability of the final design, the entire system interfaces with a common signal and data bus via clip connect jumpers. Additionally the board includes mounting holes to allow the entire system to be mounted to a piece of wood for stronger final design construction.

The board itself houses 4 16 bit registers, a single multiplexer that is addressed to each board using Dip switches, and a clocked input signal controller for each register. Overall this design delivers significant improvements in regards to the integrity of the connections, reducing cross talk, and reducing the time and error margin needed to individually solder the connections.

Design Differences for Build 2

The design diverges in a few key areas to optimize performance, and board sprawl. The first difference I made to the actual 4-bit register board is that I integrated single bit tristate buffer directly at the output of each bit, instead of the 16-bit tristate buffer on a single separate board that I used in build 1. This reduced the number of PCBs I had to order, and significantly reduced the amount of empty space on the board.

Additionally as I had done in the optimized register design of build 1 I also included board external to the 4-bit register board (but still on the container board) that handles the register clocking (generates an input clock based on load and reset signals). I included this as each 16 bit register shares a single LOAD and OUT enable signal, so there was no need to repeat the select logic for each 4 bit panel. This optimization reduced the numbers of transistors by a factor of 4 for each board.

To select the OUT and LOAD functionality of each register the design implements 2 sets of 5 bit addresses to select for both LOAD and OUT operations for a maximum of 32 registers in the CPU. Additionally there is a global LOAD and OUT signal so each board knows to do the address comparison only when these are high (otherwise register 00000 will always be actively loading and outputting when no register is meant to be active). With this scheme since each container board holds 4 16-bit register they are selected using the upper 3 bits of the LOAD and OUT signal, then the four individual register are selected using the lower 2 bits. For example if a container board is set to an address 000, the lower 2 bits select between 00000,00001,00010, and 00011.

The address multiplexing is handled from a new panel on each board that features an address comparator and multiplexer. I also incorporated a 3-switch dip switch on the board, to allow the user to manually select the upper 3 bits of the container board address. The reasoning behind this design approach was to ensure that the activation of each register could be controlled without the need to create entirely new boards. By offering this level of flexibility, the system becomes more adaptable and customizable, allowing users to configure and address the registers in a straightforward manner.

The design of this board operates first by incorporating two sets of comparators, one for the LOAD signal and the other for the OUT signal. These comparators compare the upper 3 bits of the LOAD and OUT addresses received from the signal bus. When the global output or load signal goes high, the board becomes active, signifying that the control logic is attempting to access the board with a specific address. The specific board then becomes active when the signal bus controlled LOAD and OUT addresses match the unique 3 bits of the board’s address.

To carry out this address matching, XOR gates are employed in the comparator design. These XOR gates output a 1 when the two input bits differ, which helps to identify variations between the internal address bits and the signal address bits.

The results from the XOR gates are then fed into a NOR gate. The NOR gate only produces a high output when all the XOR gate outputs are 0, indicating that all the internal address bits and the signal address bits are the same. This is crucial to ensure the correct board is being accessed.

Finally, the NOR gate’s output is passed through a NAND gate together with the global signal. This arrangement ensures that the registers on the board will only be activated when the global enable signal is high, maintaining synchronization within the system.

The second part of the design involves the implementation of the actual multiplexer, responsible for selecting between the 4 individual registers on the board using the lower 2 address bits of the load and output signals. The multiplexer itself is designed using four NOR gates, which perform the selection process based on the input and inverted input address bits.

Aside from the logical comparison and multiplexing the board also includes 2 sets of 4 LEDs to indicate which registers are actively LOADing from the bus, and which registers are OUTputting to the bus. It also includes 3 LEDs to show the user configured address of the entire board (as set by the DIP switches). Additionally the board takes in the global reset signal and inverts it for use by the registers.

*Notice that the resistors on the 8 LEDs at the top of the board are smaller. This is because in the original design I used the wrong part number for the resistors and ended up with resistors with a much too high resistance. Because of this I had to desolder and resolder new resistors and the only resistors I had where 0805 sized instead of 1206.

Final Size Comparison from Build 1 to Build 2

The initial design consisted of 4 16-bit registers with buffered output, requiring 10 perf board panels (excluding the signal multiplexer, which wasn’t present in Build 1). This configuration occupied a significant space measuring 70 cm x 36 cm (2.3 ft x 1.2 ft), resulting in a total area of 2,520 cm^2 or 0.252 m^2.

In contrast, the Build 2 design condenses all functionalities into a single unit, spanning a mere 22.5 cm x 17.5 cm (0.73 ft x 0.57 ft) and occupying a total area of 393.75 cm^2 or 0.0394 m^2.

The optimized Build 2 design, therefore, constitutes a remarkable reduction to 15.625% of the size of Build 1, and this is without even considering any additional space the multiplexer might have occupied in the original design. This impressive size reduction illustrates a significant advancement in efficiency and space utilization, making Build 2 a notable improvement over its predecessor.

Conclusion

Through careful examination, it becomes evident that the Build 2 optimizations, encompassing reductions in component size, refined design strategies, and the use of surface-mounted components, have create a compact and efficient design. Notably, this transformation has not only achieved significant size reduction but has also facilitated substantially more stable connections between individual elements, and more reliable and predictable output during testing.